zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 86
zl50110gag2
Manufacturer Part Number
zl50110gag2
Description
1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50110GAG2.pdf
(110 pages)
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11.3
These parameters are based on the Multi-Vendor Integration Protocol (MVIP) specification for an H-MVIP Bus,
Release 1.1a (1997).
Positive transitions of TDM_C2 are synchronous with the falling edges of TDM_C4 and TDM_C16. The signals
TDM_C2, TDM_C4 and TDM_C16 correspond with pins TDM_CLKi. The signals TDM_F0 correspond with pins
TDM_F0i. The signals TDM_HDS correspond with pins TDM_STi and TDM_STo.
TDM_C2 Period
TDM_C2 High
TDM_C2 Low
TDM_C4 Period
TDM_C4 High
TDM_C4 Low
TDM_C16 Period
TDM_C16 High
TDM_C16 Low
TDM_HDS Output Delay
TDM_HDS Output Delay
TDM_HDS Output to HiZ
TDM Interface Timing - H-MVIP
TDM_D Output
TDM_FRAME
TDM_D Input
Parameter
TDM_C8
Ts 127 Bit 8
Ts 127 Bit 8
Table 32 - TDM H-MVIP Timing Specification
Symbol
t
t
t
t
t
t
t
t
t
t
C16P
C16H
C16L
C2H
C4H
t
t
HZD
C2P
C2L
C4P
C4L
PD
PD
Figure 31 - H.110 Timing Diagram
t
FS
ZL50110/11/12/14
t
Zarlink Semiconductor Inc.
DOZ
487.8
243.9
Min.
60.9
220
220
110
110
30
30
t
ZDO
t
t
-
-
-
FP
t t
86
C8H
t
DV
t
FH
t
Ts 0 Bit 1
C8P
t
DIV
488.3
244.1
Typ.
Ts 0 Bit 1
61.0
-
-
-
-
-
-
-
-
-
t t
C8L
488.8
244.4
Max.
61.1
268
268
134
134
100
31
31
30
30
t
DOD
Ts 0 Bit 2
Ts 0 Bit 2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
At
8.192 Mbps
At
2.048 Mbps
Data Sheet
Notes
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