zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 56
zl50110gag2
Manufacturer Part Number
zl50110gag2
Description
1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50110GAG2.pdf
(110 pages)
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5.0
The ZL50110/11/12/14 family provides the data-plane processing to enable constant bit rate TDM services to be
carried over a packet switched network, such as an Ethernet, IP or MPLS network. The device segments the TDM
data into user-defined packets, and passes it transparently over the packet network to be reconstructed at the far
end. This has a number of applications, including emulation of TDM circuits and packet backplanes for TDM-based
equipment.
Note: The ZL50110/11/12/14 does not support the transmission or reception of jumbo packets, or packet sizes
larger than 1522 bytes.
5.1
A diagram of the ZL50110/11/12/14 device is given in Figure 13, which shows the major data flows between
functional components.
Block Diagram
Functional Description
equipment
TDM
Data Flows
Control Flows
constant bit rate
TDM link
Recovery
Interface
Clock
TDM
Figure 13 - ZL50110/11/12/14 Data and Control Flows
Figure 12 - ZL50110/11/12/14 Family Operation
TDM-Packet
conversion
interworking
Assembly
Formatter
ZL5011x
Payload
Control
Transparent data flow between TDM equipment
function
DMA
TDM
On-chip RAM and SSRAM Interface Controller
Motorola PowerQUICC
ZL50110/11/12/14
Zarlink Semiconductor Inc.
Memory Management Unit
Off-chip Packet Memory
0-8 MBytes SSRAM
packet switched
network
Manager
Protocol
Central
Engine
Task
56
Host Interface
TM
Compatible
TDM-Packet
conversion
interworking
ZL5011x
function
Transmit
Receive
Packet
Packet
constant bit rate
JTAG Interface
JTAG Test
Controller
TDM link
Interface
Admin.
Packet
Triple
MAC
equipment
TDM
Data Sheet
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