zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 83

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

In synchronous mode the clock must be within the locking range of the DPLL to function correctly (± 245 ppm). In
asynchronous mode, the clock may be any frequency.
TDM_CLKI (2.048 MHz)
TDM_CLKI (4.096 MHz)
TDM_CKLI
TDM_STo
TDM_STi
TDM_F0i
TDM_STo
TDM_STi
TDM_F0i
Channel 127 bit 1
Figure 27 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps
Figure 28 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps
Channel 127 bit 1
t
STIS
Channel 31 Bit 0
t
STIH
Ch 31 Bit 0
ZL50110/11/12/14
t
Zarlink Semiconductor Inc.
FOIW
Channel 127 bit 0
t
STOD
t
Channel 127 bit 0
FOIS
t
STIS
t
STOD
t
STIH
83
t
C4IP
t
FOIH
Channel 0 Bit 7
t
Ch 0 Bit 7
C2IP
t
FOIS
t
t
t
STIS
STIH
C16IP
Channel 0 bit 7
t
t
FOIH
STOD
t
STIS
Channel 0 bit 7
t
STIH
Ch0 bit7
t
STOD
Channel 0 Bit 6
Channel 0 bit 6
t
Ch 0 Bit 6
STOD
Data Sheet