zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 97

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

CPU_ADDR[23:2]
CPU_DATA[31:0]
CPU_ADDR[23:2]
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TS_ALE
CPU_CLK
CPU_WE
CPU_CS
CPU_OE
CPU_TA
CPU_CLK
CPU_WE
CPU_OE
CPU_CS
CPU_TA
NOTE 1: CPU_DATA is valid when CPU_TA is asserted. CPU_DATA will remain valid while both CPU_CS
and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted.
CPU_CS and CPU_OE must BOTH be asserted to enable the CPU_DATA output.
NOTE 2: CPU_TS_ALE is no more than one clock cycle width and it can be delayed by one clock cycle from
CS assertion.
NOTE 3: The CPU_TA maximum assertion time is 4 µs.
NOTE 1: Following assertion of CPU_TA, CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS
until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is
finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed.
NOTE 2: CPU_TS_ALE is no more than one clock cycle width and it can be delayed by one clock cycle from
CS assertion.
NOTE 3:The CPU_TA maximum assertion time is 4 µs.
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CSS
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Figure 44 - CPU Write - MPC8260
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Figure 43 - CPU Read - MPC8260
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ZL50110/11/12/14
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Zarlink Semiconductor Inc.
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Data Sheet
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