zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 93

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

11.6.5
Note1:
ZLAN-239 for proper operation when using the TBI interface.
GTXCLK period
GTXCLK high wide time
GTXCLK low wide time
TXD[9:0] Output Delay
(GTXCLK rising edge)
RCB0/RBC1 period
RCB0/RBC1 high wide time
RCB0/RBC1 low wide time
RCB0/RBC1 rise time
RCB0/RBC1 fall time
RXD[9:0] setup time (RCB0
rising edge)
RXD[9:0] hold time (RCB0
rising edge)
REFCLK period
REFCLK high wide time
REFCLK low wide time
These measurements were obtained through simulation and lab measurement using a 10pF load. See Application Note,
Signal_Detect
TBI Interface Timing
Parameter
GTXCLK
TXD[9:0]
/I/
/S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/ /I/
t
GC
Symbol
Figure 38 - TBI Transmit Timing Diagram
t
t
t
t
t
t
t
t
t
t
t
t
t
t
GC
GH
RC
RH
RR
DH
GL
DV
RL
RF
DS
FC
FH
Table 39 - TBI Timing - 1000 Mbps
FL
ZL50110/11/12/14
Zarlink Semiconductor Inc.
t
DV
Min.
7.5
2.5
2.5
0.1
7.5
2.5
2.5
15
5
5
2
1
-
-
93
1000 Mbps
Typ.
16
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
8.5
2.4
8.5
17
2
2
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load = 10 pF
Data Sheet
Note 1
Notes