zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 31

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

3.2
All PAC Interface signals are 5 V tolerant
All PAC Interface outputs are high impedance while System Reset is LOW.
TDM_CLKiP
TDM_CLKiS
PLL_PRI
PLL_SEC
PAC Interface
Signal
I/O
OT
OT
I D
I D
C1
D3
U1
V1
Table 7 - PAC Interface Package Ball Definition
Package Balls
ZL50110/11/12/14
Zarlink Semiconductor Inc.
31
Primary reference clock input. Should be
driven by external clock source to provide
locking reference to internal / optional
external DPLL in TDM master mode. Also
provides PRS clock for RTP timestamps in
synchronous modes.
Acceptable frequency range: 8 kHz -
34.368 MHz (generally should be between
10 MHz and 25 MHz as per ITU-T Y.1413.
Secondary reference clock input. Backup
external reference for automatic switch-over
in case of failure of TDM_CLKiP source.
Primary reference output to optional
external DPLL.
Multiplexed & frequency divided reference
output for support of optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
Secondary reference output to optional
external DPLL Multiplexed & frequency
divided reference output for support of
optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
Description
Data Sheet