ppc440gr-3jb667cz Applied Micro Circuits Corporation (AMCC), ppc440gr-3jb667cz Datasheet - Page 82

• Manufacturer Part Number: ppc440gr-3jb667cz
• Description: Powerpc 440gr Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

Example 1:
If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage
1 data is sampled at
to the PPC440GR, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary to
sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to
allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example, T
controlled and set by the software.
Figure 12. DDR SDRAM Read Cycle Timing—Example 1
82
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
Data in Stage 1 D
Data out Stage 1
Data in at RDSP
DQS Stage 1 C
Data out RDSP
with no ECC
Data at pin
DQS at pin
PLB Clock
T
DIN
(1)
. Except for small, low frequency memory systems with the memory located physically close
High
Low
High
Low
T
High
Low
T
D0
SIN
T
D0
T
T
T
P
T
T
SIN
P
DIN
T
D0
= Propagation delay through FFs
= Propagation delay, Stage 1 input to RDSP input w/o ECC
= Delay from DQS at package pin to C on Stage 1 FF.
T
= Delay from data at package pin to D on Stage 1 FF.
D1
D0
P
D1
D0
D1
(1)
D0
D1
D2
D2
D0
D1
D2
440GR – PPC440GR Embedded Processor
D3
D2
D3
D2
D3
D2
D3
D2
D3
AMCC Proprietary
T
is