ppc440gr-3jb667cz Applied Micro Circuits Corporation (AMCC), ppc440gr-3jb667cz Datasheet - Page 57
ppc440gr-3jb667cz
Manufacturer Part Number
ppc440gr-3jb667cz
Description
Powerpc 440gr Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
1.PPC440GR-3JB667CZ.pdf
(88 pages)
- Current page: 57 of 88
- Download datasheet (2Mb)
Table 9. Signal Functional Description (Sheet 5 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
440GR – PPC440GR Embedded Processor
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldReq
HoldPri
PerClk
UART Peripheral Interface
UARTSerClk
UARTn_Rx
UARTn_Tx
UARTn_DCD
UARTn_DSR
UARTn_CTS
UARTn_DTR
UARTn_RTS
UARTn_RI
IIC Peripheral Interface
IIC0SClk
IIC0SData
IIC10SClk
IIC1SData
Signal Name
UART Receive data.
Bus Request. Used when the PPC440GR needs to regain
control of peripheral interface from an external master.
External Acknowledgement. Used by the PPC440GR to
indicate that a data transfer occurred.
External Request. Used by an external master to indicate it is
prepared to transfer data.
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
Hold Acknowledge. Used by the PPC440GR to transfer
ownership of peripheral bus to an external master.
Hold Request. Used by an external master to request
ownership of the peripheral bus.
Hold Primary. Used by an external master to indicate the
priority of a given external master tenure.
Peripheral Clock. Used by an external master and by
synchronous peripheral slaves.
Serial clock input that provides an alternative to the internally
generated serial clock. Used in cases where the allowable
internally generated clock rates are not satisfactory.
UART Transmit data.
UART Data Carrier Detect.
UART Data Set Ready.
UART Clear To Send.
UART Data Terminal Ready.
UART Request To Send.
UART Ring Indicator.
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
Description
Preliminary Data Sheet
Revision 1.19 – May 07, 2008
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Type
Notes
1, 5
1, 4
1, 4
1, 6
1, 2
1, 2
1
6
6
1
2
2
57
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