ppc440gr-3jb667cz Applied Micro Circuits Corporation (AMCC), ppc440gr-3jb667cz Datasheet - Page 54

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ppc440gr-3jb667cz

Manufacturer Part Number
ppc440gr-3jb667cz
Description
Powerpc 440gr Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
Table 9. Signal Functional Description (Sheet 2 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
54
DDR SDRAM Interface
BA0:1
BankSel0:3
CAS
ClkEn
DM0:3
DM8
DQS0:3
DQS8
ECC0:7
MemAddr00:12
MemClkOut0
MemClkOut0
MemData00:31
MemSelfRef
RAS
WE
S
S
VREF1
VREF2A:B
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
Signal Name
Bank Address supporting up to four internal banks.
Clock Enable.
Memory address bus.
Memory data bus.
Self refresh.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
Memory write data byte lane masks. DM8 is the byte lane
mask for the ECC byte lane.
Byte lane data strobe. DQS8 is the data strobe for the ECC
byte lane.
ECC check bits 0:7.
Subsystem clock.
Row Address Strobe.
Write Enable.
SSTL reference voltage.
Supplemental SSTL reference voltage.
Description
440GR – PPC440GR Embedded Processor
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
Volt ref receiver
(supplemental)
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
3.3V tolerant
2.5V CMOS
Volt ref pin
Diff driver
Type
AMCC Proprietary
Notes
5

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