ppc440gr-3jb667cz Applied Micro Circuits Corporation (AMCC), ppc440gr-3jb667cz Datasheet - Page 59

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ppc440gr-3jb667cz

Manufacturer Part Number
ppc440gr-3jb667cz
Description
Powerpc 440gr Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
Table 9. Signal Functional Description (Sheet 7 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
440GR – PPC440GR Embedded Processor
System Interface
SysClk
SysErr
SysReset
Halt
TmrClk1
TmrClk2
GPIO00:63
TestEn
RcvrInh
ModeCtrl
LeakTest
RefEn
DrvrInh1:2
PSROOut
Signal Name
Main system clock input.
Set to 1 when a machine check is generated.
Module characterization and screening.
Main system reset. External logic can drive this bidirectional
pin low (minimum of 16 cycles) to initiate a system reset. A
system reset can also be initiated by software. Implemented as
an open-drain output (two states; 0 or open circuit).
Halt from external debugger.
Processor timer external input clock.
This signal must be connected to a clock. It can be connected
to any available clocking signal in the frequency range of
32kHz to 100MHz including TmrClk1.
General purpose I/O 0 through 63. To access these functions,
software must set DCR register bits.
Test Enable.
Receiver Inhibit. Active only when TestEn is active. Used for
manufacturing test only.
Mode Control. Active only when TestEn is active. Used for
manufacturing test only.
Leakage Test. Active only when TestEn is active. Used for
manufacturing test only.
Reference Enable. Active only when TestEn is active. Used for
manufacturing test only.
Driver Inhibit. Active only when TestEn is active. Used for
manufacturing test only.
Description
Preliminary Data Sheet
Clock
Revision 1.19 – May 07, 2008
I/O
I/O
I/O
O
O
I
I
I
I
I
I
I
I
I
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
3.3V LVTTL
3.3V LVTTL
Perf screen
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
ring osc
Type
Notes
1, 2
1, 2
1, 3
3
59

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