ppc440gr-3jb667cz Applied Micro Circuits Corporation (AMCC), ppc440gr-3jb667cz Datasheet - Page 58

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ppc440gr-3jb667cz

Manufacturer Part Number
ppc440gr-3jb667cz
Description
Powerpc 440gr Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
Table 9. Signal Functional Description (Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
58
NAND Flash Interface
NFALE
NFCE0:3
NFCLE
NFRdyBusy
NFREn
NFWEn
Serial Peripheral Interface
SCPClkOut
SCPDI
SCPDO
Interrupts Interface
IRQ0:4
IRQ5
IRQ6:9
JTAG Interface
TCK
TDI
TDO
TMS
TRST
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
Signal Name
Address Latch Enable.
Clock output.
Data In.
Data output.
External interrupt requests 0 through 4.
External interrupt request 5.
External interrupt requests 6 through 9.
Chip Enable (multiplexed with the PerCS0:3 signals).
Command Latch Enable.
Ready/Busy.
Indicates status of device during program erase or page read.
This signal is wire-or connected from all NAND Flash devices.
Read Enable strobe.
Write Enable strobe.
Test Clock.
Test Data In.
Test Data Out.
Test Mode Select.
Test Reset.
Note: Must be asserted low during a power-on system reset in
order to reset the JTAG interface. If the JTAG interface is not
reset, the processor may not boot.
Description
440GR – PPC440GR Embedded Processor
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
3.3V tolerant
3.3V LVTTL
3.3V LVTTL
2.5V CMOS
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
w/pull-up
w/pull-up
w/pull-up
w/pull-up
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Type
AMCC Proprietary
Notes
2
2
2
1
1
1
1
1
5
4

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