ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 3

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Features
Embedded Core Features
• Implemented in an ORCA Series 4 FPGA.
• Allows a wide range of high-speed backplane applications, including SONET transport and termination.
• No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz—106 MHz clock,
• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external
• Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8
• HSI function uses Lattice’s 850 Mbits/s serial interface core. Rates from 126 Mbits/s to 850 Mbits/s are sup-
• LVDS I/Os compliant with EIA
• Low-power 1.5 V HSI core.
• Low-power LVDS buffers.
• Programmable STS-3, and STS-12 framing.
• Independent STS-3, and STS-12 data streams per quad channels.
• 8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic.
• On-chip, Phase-Lock Loop (PLL) clock meets (type B) jitter tolerance specification of ITU-T recommendation
• Powerdown option of HSI receiver on a per-channel basis.
• HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state.
• Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above
• In-band management and configuration through transport overhead extraction/insertion.
• Supports transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted.
• Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks.
• Built-in boundry scan ( IEEE
• FIFOs align incoming data across all eight channels (two groups of four channels or four groups of two channels)
• 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection
• ORCA FPGA soft intellectual property core support for a variety of applications.
• Programmable Synchronous Transport Module (STM) pointer mover bypass mode.
• Programmable STM framer bypass mode.
• Programmable Clock and Data Recovery (CDR) bypass mode (clocked LVDS High-Speed Interface).
• Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channels
and a frame pulse.
clocks.
Gbits/s (full duplex).
ported.
on-board termination to allow long-haul driving of backplanes.
G.958.
rates.
for both SONET scrambling. Optional ability to bypass alignment FIFOs.
switching applications. STS-192 and above rates are supported through multiple devices.
with redundancy on a single device.
®
1149.1 JTAG).
®
-644 support hot insertion. All embedded LVDS I/Os include both input and output
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ORCA ORT8850 Data Sheet