ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 61

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Table 19. Memory Map Descriptions (Continued)
Lattice Semiconductor
Absolute
Address
30012
30013
30014
30015
30016
(0x)
[2-7]
[2-7]
[4-7]
[0:7]
[0:1]
[2:3]
[4-7]
Bit
[0]
[1]
[0]
[1]
[0]
[1]
[2]
[3]
Type
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
-
-
-
-
frame offset error
flag
write to locked reg-
ister error flag
Not Used
frame offset error
enable
write to locked reg-
ister for error
enable
Not Used
BA alarm
BB alarm
BC alarm
BD alarm
Not Used
Not Used
STM A mode con-
trol
STM B mode con-
trol
Not Used
Name
Reset
Value
(0x)
N/A
00
0
0
0
0
0
0
0
0
0
0
0
0
0
61
If in the receive direction the phase offset between any two
channels exceeds 17 bytes, then a frame offset error event will
be issued. This condition is continuously monitored.
Write a “1” to clear this bit
If the core memory map has not been unlocked (by writing to
the lock registers), and any address other than the lockreg reg-
isters or scratch pad register is written to, then a “write to locked
register” event will be generated.
Write a “1” to clear this bit
Frame offset error flag enable.
0 = not enable
1 = enable
Write to locked register error flag enable
0 = not enable
1 = enable
Consolidation alarm for channel BA
0 = no alarm
1 = alarm
Consolidation alarm for channel BB
0 = no alarm
1 = alarm
Consolidation alarm for channel BC
0 = no alarm
1 = alarm
Consolidation alarm for channel BD
0 = no alarm
1 = alarm
00 - Quad STS-12 or STS-48.
10 - Quad STS-3.
00 - Quad STS-12 or STS-48.
10 - Quad STS-3.
ORCA ORT8850 Data Sheet
Description