ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 47

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
FPGA/Embedded Core Interface Signals
Table 15. FPGA/Embedded Core Interface Signals
Table 14. Register Settings for Bypass Mode (Continued)
Common Interface Signals
FPGA_SYSCLK
0x30021
0x30039
0x30051
0x30069
0x30081
0x30099
0x300B1
0x300C8
0x30023
0x3003B
0x30053
0x3006B
0x30083
0x3009B
0x300B3
0x300CB
0x30037
0x3004F
0x30067
0x3007F
0x30097
0x300AF
0x300C7
0x300DF
Note: To select between full, half and quad rate modes, registers 0x300E1 and 0x300E2 are used. See the memory map for details on these
registers.
FPGA/Embedded Core
Interface Signal Name
Register Address
xx=[AA,…,BD]
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x30
0x30
0x30
0x30
0x30
0x30
0x30
0x30
0x44
0x44
0x44
0x44
0x44
0x44
0x44
0x44
ORT8850 FPGA/Embedded Core Interface Signals - SONET Blocks
Input (I) to or Output (O)
Value
from Core
O
Channel AA in transparent mode
Channel AB in transparent mode
Channel AC in transparent mode
Channel AD in transparent mode
Channel BA in transparent mode
Channel BB in transparent mode
Channel BC in transparent mode
Channel BD in transparent mode
Channel AA - Do not insert A1/A2 or B1
Channel AB - Do not insert A1/A2 or B1
Channel AC - Do not insert A1/A2 or B1
Channel AD - Do not insert A1/A2 or B1
Channel BA - Do not insert A1/A2 or B1
Channel BB - Do not insert A1/A2 or B1
Channel BC - Do not insert A1/A2 or B1
Channel BD - Do not insert A1/A2 or B1
Channel AA - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
Channel AB - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
Channel AC - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
Channel AD - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
Channel BA - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
Channel BB - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
Channel BC - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
Channel BD - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
Local reference clock from the core to the FPGA. All of the transmit
data is captured on this clock edge inside the ORT8850 core. If
using the alignment FIFO all of the parallel data from the ort8850
core will also be clocked from this clock. This signal uses an ORCA
Series4 primary clock route.
47
Description
Signal Description
ORCA ORT8850 Data Sheet