ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 56

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Powerdown Mode
Powerdown mode will be entered when the corresponding channel is disabled. Channels can be independently
enabled or disabled under software control.
Parallel data bus output enable and TOH serial data output enable signals are made available to the FPGA logic.
The HSI macrocell’s corresponding channel is also powered down. The device will power up with all eight channels
in powerdown mode.
Protection Switching
There is built-in protection switching between the SERDES channels, in the receive direction of the ORT8850. Pro-
tection switching allows pairs of SERDES channels to act as main and protect data links, and to switch between the
main and protect links via a control register or FPGA interface port. There are two types of protection switches: par-
allel and LVDS.
Parallel protection switching takes place just before the FPGA interface ports, and after the alignment FIFO. The
alignment FIFO must be used for this type of protection switching. It is possible to bypass the pointer inter-
preter/mover and still use the parallel protection switching. In this mode, SERDES channels AA and AB are used
as main and protect. When selected for main, channel AA is used to provide data on interface ports AA. When
selected for protect, channel AB is used to provide data on FPGA interface ports AA. The same scheme is used for
channel groupings AC/AD, BA/BB, and BC/BD
There are two ways to control the parallel protection switching, interface signal and software control. On the FPGA
interface, there are 4 input signals to the ORT8850 core that will select between a main and a protect channel.
When using the interface signal to control protection switching, only the parallel data is switched; the serial TOH
data outputs are not switched.
Software control will switch both the parallel data and the serial TOH data outputs to the FPGA. The software con-
trol register is found at 0x30009 in the memory map (Table 19).
Table 17. Register Settings, Parallel Protection Switching
LVDS protection switching takes place at the LVDS buffer before the serial data is sent into the Data Recovery
(CDR). The selection is between the main LVDS buffer and the protect LVDS buffer. The work LVDS buffers are
TXDxx_W_[P:N], while the protect LVDS buffers are TXDxx_P_[P:N]. When operating using the LVDS buffers
(default), no status information is available on the protect LVDS buffers since the serial stream must reach the
SONET framer before status information is available on the data stream. The same is also true for the work LVDS
buffers when operating with the protect buffers.
There are two ways to control the LVDS protection switching, interface and software control. On the FPGA inter-
face, there are eight input signals to the ORT8850 core that will select between the work and protect LVDS buffers.
Table 18. LVDS Protection Switching
FPGA Interface Signal
FPGA Interface Signal
PROT_SWITCH_BC
PROT_SWITCH_AA
PROT_SWITCH_AC
PROT_SWITCH_BA
LVDS_PROT_AA
LVDS_PROT_AB
LVDS_PROT_AC
LVDS_PROT_AD
Channel AD gets TXD_AD_W_[P:N]
Channel AA gets TXD_AA_W_[P:N]
Channel AB gets TXD_AB_W_[P:N]
Channel AC gets TXD_AC_W_[P:N]
Channel BD data on DOUTBC
Channel BB data on DOUTBA
Channel AB data on DOUTAA
Channel AD data on DOUTAC
When ‘0’
When ‘0’
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ORCA ORT8850 Data Sheet
Channel AC gets TXD_AC_P_[P:N]
Channel AD gets TXD_AD_P_[P:N]
Channel AA gets TXD_AA_P_[P:N]
Channel AB gets TXD_AB_P_[P:N]
Channel BC data on DOUTBC
Channel BA data on DOUTBA
Channel AA data on DOUTAA
Channel AC data on DOUTAC
When ‘1’
When ‘1’