ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 52

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
In the case shown in Figure 28 the alignment FIFO is used and all timing is with respect to the single reference
clock, which is routed through the FPGA as a primary clock. The capturing clock edge occurs after the launch of
the next data byte, so hold time margin is of concern and an acceptably margin should be verified. Launched data
has nearly a full clock period to become stable at the capture latch, so setup margin should not be a problem. Mov-
ing the capture to the rising clock edge might give a setup time margin problem.
Figure 28. Half Cycle, Alignment Mode Output Configuration and Timing (-1 Speed Grade)
FPGA_SYSCLK
FPGA_CLK
DOUTxx[7:0]
FPGA_CLK
FPGA
Logic
ASB_CLK
Primary Clock
+
tprop_min = - 0.8
-1.4
0.0
D
3.0 ns
Hold
3.0
3.3
Δ Δ Δ Δ t
4.7
a.) Configuration
Launch
tprop_max = 2.4
FPGA_SYSCLK
Note: xx = [AA, AB, ... BD]
DOUTxx[7:0]
b.) Timing (times in ns.)
7.7
8.0
52
9.4
Data Valid
12.7
12.4
Δ Δ Δ Δ t
1.4 ns
Capture
14.1
Q
17.1
ORCA ORT8850 Data Sheet
17.4
-
18.8
Embedded
ASB_CLK
Core