ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 32

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 15. TOH Serial Port Input Framing Signals (FPGA to Core)
Although all TOH bytes from the 12 STS-1s are transferred into the device from each serial port, not all of them get
inserted in the frame. There are three hard coded exceptions to the TOH byte insertion:
• Framing bytes (A1/A2 of all STS-1s) are not inserted from the serial input bus. Instead, they can always be
• Parity byte (B1 of STS#1) is not inserted from the serial input bus. Instead, it is always recalculated (the 11 bytes
• Pointer bytes (H1/H2/H3 of all STS-1s) are not inserted from the serial input bus. Instead, they always flow trans-
Except for the above hardcode exceptions, the source of some TOH bytes can be controlled by bits in the control
registers. The 12 STS-1 bytes forming a single STS-12 TOH header block are controlled as a whole. When config-
ured to be in the transparent mode, the specific bytes must flow transparently from the parallel input. The 15 over-
head bytes that can be controlled on a per STS-1 basis are the following:
• K1 and K2 bytes of the 12 STS-1s (24 bytes)
• S1 and M0 bytes of the 12 STS-1s (24 bytes)
• E1, F1, E2 bytes of the STS-1s (36 bytes)
• D1 through D12 bytes of the STS-1s (144 bytes)
The C1(J0) and B2 bytes (unshaded in the following table) are also passed through transparently from the parallel
bus to the serial link.
Table 10 shows the order in which data is transferred to the serial LVDS output, starting with the most significant bit
of the first A1 byte. The first bit of the first byte is replaced by an even parity check bit over all TOH bytes from the
previous TOH frame. The source for the TOH bytes in the Serial TOH insert mode is summarized in the table.
regenerated.
following B1 are replaced with all zeros).
parently from parallel input to LVDS output.
Row n-1
Row n
Etc.
STS1
For
#1
A1 A1
B1 B1
STS1
For
#2
Data on Parallel Input Bus
. . .
. . .
Transparent Insert TOH
STS1
#12
For
A1 A2
B1 E1
STS1
For
#1
. . .
. . .
STS1
32
#12
For
J0
F1
4 TOH_CLK Cycles
Guardband of
SPE Data on Parallel Input Bus
D1, D2 and D3 for all 12 STS1's
B1, E1 and F1 for all 12 STS1's
Window to Send TOH Bytes
Window to Send TOH Bytes
on Serial Input Bus
on Serial Input Bus
ORCA ORT8850 Data Sheet
. . .
. . .
4 TOH_CLK Cycles
Guardband of