k4b2g0846b Samsung Semiconductor, Inc., k4b2g0846b Datasheet - Page 16

• Manufacturer Part Number: k4b2g0846b
• Description: 2gb B-die Ddr3 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

K4B2G04(08/16)46B
8.3 AC and DC Logic Input Levels for Ditterential Signals
8.3.1 Differential signal definition
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 9 ]
Notes:
1. Used to define a differential signal slew-rate.
2. for CK - CK use V
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
[ Table 10 ] Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS.
reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
limits (V
Specification ".
V
V
Symbol
IHdiff
ILdiff
V
V
IHdiff
ILdiff
IH
(AC)
(AC)
Differential AC and DC Input Levels
(DC) max, V
Slew Rate [V/ns]
IH
> 4.0
< 1.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
/V
IL
IL
differential input high ac
(AC) of ADD/CMD and V
(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Reter to "overshoot and Undersheet
differential input low ac
differential input high
differential input low
Parameter
Figure 2 : Definition of differential ac-swing and "time above ac level" tDVAC
V
V
IL
IH
.DIFF.AC.MAX
.DIFF.AC.MIN
V
V
IL
IH
.DIFF.MAX
.DIFF.MIN
REFCA
0.0
tDVAC [ps] @ |V
; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use V
min
75
57
50
38
34
29
22
13
0
0
2 x (V
half cycle
Page 16 of 61
IH
note 3
note 3
+0.2
min
(AC)-V
IH/Ldiff
tDVAC
DDR3-800/1066/1333/1600
REF
(AC)| = 350mV
)
max
-
-
-
-
-
-
-
-
-
-
2 x (V
tDVAC
REF
note 3
note 3
max
-0.2
- V
tDVAC [ps] @ |V
IL
(AC))
min
175
170
167
163
162
161
159
155
150
150
time
IH
2Gb DDR3 SDRAM
/V
Rev. 1.0 December 2008
IL
(AC) of DQs and V
IH/Ldiff
unit
V
V
V
V
(AC)| = 300mV
REFDQ
max
-
-
-
-
-
-
-
-
-
-
Note
; if a
1
1
2
2