vpx3224d ETC-unknow, vpx3224d Datasheet - Page 16

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

16
–10
–20
–30
VPX 3225D, VPX 3224D
2.5.2. Skew Correction
The VPX delivers orthogonal pixels with a fixed clock
even in the case of non-broadcast signals with substan-
tial horizontal jitter (VCRs, laser disks, certain portions
of the 6 o’clock news...).
This is achieved by highly accurate sync slicing com-
bined with post correction. Immediately after the analog
input is sampled, a horizontal sync slicer tracks the posi-
tion of sync. This slicer evaluates, to within 1.6 ns, the
skew between the sync edge and the edge of the pixel-
clock. This value is passed as a skew on to the phase
shift filter in the resizer. The skew is then treated as a
fixed initial offset during the resizing operation.
The skew block in the resizer performs programmable
phase shifting with subpixel accuracy. In the luminance
path, a linear interpolation filter provides a phase shift
between 0 and 31/32 in steps of 1/32. This corresponds
to an accuracy of 1.6 ns. The chrominance signal can be
shifted between 0 and 7/8 in steps of 1/8.
2.5.3. Peaking and Coring
The horizontal resizer comes with an extra peaking filter
for sharpness control. The center frequency of the peak-
ing filter is automatically adjusted to the image size in
512 steps. The peaking value to each center frequency
can be controlled by the user with up to eight steps via
FP-RAM 0x126/130. Fig. 2–14 shows the magnitude re-
sponse of the eight steps of the peaking filter corre-
sponding to an image size of 320 pixels.
After the peaking filter, an additional coring filter is imple-
mented to the horizontal resizer. The coring filter sub-
tracts 0, 1/2, 1, or 2 LSBs of the higher frequency part of
the signal. Note, that coring can be performed indepen-
dently of the peaking value adjustment.
Fig. 2–14: Frequency response of peaking filter
dB
10
0
0
1
2
3
4
5
MHz
6
2.5.4. YCbCr Color Space
The color decoder outputs luminance and one multi-
plexed chrominance signal at a sample clock of
20.25 MHz. Active video samples are flagged by a sepa-
rate reference signal. Internally, the number of active
samples is 1080 for all standards (525 lines and 625
lines). The representation of the chroma signals is the
ITU-R 601 digital studio standard.
In the color decoder, the weighting for both color differ-
ence signals is adjusted individually. The default format
has the following specification:
– Y = 224*Y + 16 (pure binary),
– C
– C
2.5.5. Video Adjustments
The VPX provides a selectable gain (contrast) and offset
(brightness) for the luminance samples, as well as addi-
tional noise shaping. Both the contrast and brightness
factors can be set externally via I
RAM 0x127,128,131, and 132. Fig. 2–15 gives a func-
tional description of this circuit. First, a gain is applied,
yielding a 10-bit luminance value. The conversion back
to 8-bit is done using one of four selectable techniques:
simple rounding, truncation,1-bit error diffusion, or 2-bit
error diffusion. Bit[8] in the ‘contrast’-register selects be-
tween the clamping levels 16 and 32.
In the chrominance path, Cb and Cr samples can be
swapped with bit[8] in FP-RAM 0x126 or 130. Adjust-
ment of color saturation and gain is provided via FP-
RAM 0x30–33 (see section 2.2.5.).
Fig. 2–15: Contrast and brightness adjustment
Contrast
r
b
= 224*(0.713*(R–Y)) + 128 (offset binary),
= 224*(0.564*(B–Y)) + 128 (offset binary).
I
out
= c * I
in
Truncation
Rounding
Err. Diff.
Err. Diff.
+ b
Select
1 bit
2 bit
PRELIMINARY DATA SHEET
c = 0...63/32 in 64 steps
b = –127...128 in 256 steps
Brightness
2
C serial control of FP-
FP-RAM
Registers
Micronas