vpx3224d ETC-unknow, vpx3224d Datasheet - Page 65

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vpx3224d

Manufacturer Part Number
vpx3224d
Description
Video Pixel Decoders
Manufacturer
ETC-unknow
Datasheet
Micronas
PRELIMINARY DATA SHEET
6. Control and Status Registers
The following tables give definitions for the VPX control
and status registers. The number of bits indicated for
each register in the table is the number of bits imple-
mented in the hardware, i.e. a 9-bit register must always
be accessed using two data bytes, but the 7 MSB will be
“0” on write operations and don’t care on read opera-
tions. Write registers that can be read back are indicated
in the mode column.
6.1. Overview
Address
Hex
h’00
h’01
h’02
h’03
h’35
h’36
h’37
h’38
h’AA
h’B3
h’B4
h’B5
h’B6
h’B7
h’B8
h’B9
h’BA
h’BB
h’BC
h’BD
h’C0
h’C1
h’C2
h’C5
h’C6
h’C7
h’C8
h’C9
h’CE
h’CF
h’F2
h’F8
h’F9
Number
of Bits
8
8
8
8
8
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Mode
r
r
r
r
w
w
w/r
w
r
r
r
r
r
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Function
Manufacture ID
16-bit part number
JEDEC2
FP status
FP read
FP write
FP data
Low power mode, LLC mode
soft error counter
sync status
hsync counter
read filter coefficient
read data slicer level
clock run-in and framing code don’t care mask high
clock run-in and framing code don’t care mask mid
clock run-in and framing code don’t care mask low
clock run-in and framing code reference high
clock run-in and framing code reference mid
clock run-in and framing code reference low
soft slicer level
ttx bitslicer frequency LSB
ttx bitslicer frequency MSB
filter coefficient
data slicer level
accumulator mode
sync slicer level
standard
bit error tolerance
byte count
Output Enable
Pad Driver Strength – TTL Output Pads Type A
Pad Driver Strength – TTL Output Pads Type B
I
2
C-Registers
The control register modes are
– w
– r
– w/r write/read register
– d
– v
Default values are initialized at reset. The mnemonics
used in the Micronas VPX demo software are given in
the last column.
write-only register
read-only register
register is double latched
register is latched with vsync
VPX 3225D, VPX 3224D
Group
Chip Ident.
Chip Ident.
Chip Ident.
FP Interface
FP Interface
FP Interface
FP Interface
Output
Byte Slicer
Sync Slicer
Sync Slicer
Bit Slicer
Bit Slicer
Byte Slicer
Byte Slicer
Bit Slicer
Bit Slicer
Bit Slicer
Bit Slicer
Bit Slicer
Sync Slicer
Byte Slicer
Byte Slicer
Byte Slicer
Output
Output
Output
Name
JEDEC
PARTNUM
JEDEC2
FPSTA
FPRD
FPWR
FPDAT
llc
softerrcnt
sync_stat
sync_cnt
coeff_rd
level_rd
mask
reference
soft_slicer
ttx_freq
coeff
data_slicer
accu
sync_slicer
standard
tolerance
byte_cnt
oena
driver_a
driver_b
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