vpx3224d ETC-unknow, vpx3224d Datasheet - Page 69

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

Micronas
PRELIMINARY DATA SHEET
Address
Hex
h’F8
h’F9
h’F2
h’AA
Number
of bits
8
8
8
8
Mode
w
w
w
direct
direct
direct
direct
direct
direct
direct
direct
w
Function
Pad Driver Strength – TTL Output Pads Typ A
bit [2:0] :
bit [5:3] :
bit [7:6] :
Pad Driver Strength – TTL Output Pads Typ B
bit [2:0] :
bit [5:3] :
bit [7:6] :
Output Enable
bit [0] :
bit [1] :
bit [2] :
bit [3] :
bit[4]
bit [5] :
bit [6] :
bit [7] :
Low power mode, LLC mode
bit [1:0] :
bit [2] :
bit [3] :
bit [4] :
bit [5] :
bit [6] :
(version D4 only)
bit [7] :
I
2
C-Registers VPX Back-End
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00
01
10
11
1
0
1
0
Driver strength of Port A[7:0]
Driver strength of PIXCLK, LLC, and VACT
Driver strength of Port B[7:0]
Driver strength of HREF, VREF, FIELD, and LLC2
Enable Video Port A
Enable Video Port B
Enable Pixclk Output
Enable HREF, VREF, FIELD, VACT, LLC, LLC2
no delay of OEQ input signal
latch OEQ input signal with rising edge of LLC
disable OEQ pin function
use old llc timing with long hold time
reserved (must be set to zero)
additional PIXCLK driver strength
strength = bit [5:3] | {bit [7:6], 0}
reserved (must be set to zero)
Disable / High Impedance Mode
Disable / High Impedance Mode
Disable / High Impedance Mode
Disable / High Impedance Mode
Enable LLC2 to TDO pin
(if JTAG interface is in Test-Logic-Reset State)
Disable LLC2
1 LLC cycle delay of OEQ input signal (if bit [6] = 1)
don’t latch OEQ input signal
Low power mode
active mode, outputs enabled
outputs tri-stated; clock divided by 2, I
outputs tri-stated; clock divided by 4, I
outputs tri-stated; clock divided by 8, I
I
connect LLC2 to TDO pin
connect bit[4] to TDO pin
if bit[3] then bit[4] defines LLC2 polarity
else bit[4] is connected to TDO pin
switch-off slicer
(if slowpow = 1 then all slicer registers are reset).
use new llc timing with shorter hold time
2
C reset
Output
VPX 3225D, VPX 3224D
2
2
2
C full speed
C full speed
C < 100 kbit/s
Default
Name
DRIVER_A
stra1
stra2
stra3
DRIVER_B
strb1
strb2
OENA
aen
ben
clken
zen
llc2en
oeqdel
latoeq
oeq_dis
LLC
lowpow
iresen
llc2
llc2_pol
slowpow
oldllc
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