vpx3224d ETC-unknow, vpx3224d Datasheet - Page 70

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

70
VPX 3225D, VPX 3224D
Table 6–3: I
Address
Hex
h’C8
h’B4
h’B5
h’C0
h’C1
h’C2
h’C5
h’C6
2
Number
of bits
8
8
8
8
8
8
8
8
C-Registers VPX Slicer
Mode
w
r
r
w
w
w
w
w
Function
sync slicer
bit [6:0] :
bit [7] :
sync status
bit [5:0] :
bit [6] :
bit [7] :
hsync counter
bit [7:0] :
soft slicer
bit [6:0] :
bit [7] :
ttx bitslicer frequency LSB
ttx bitslicer frequency MSB
bit [10:0] : Freq
bit [11] :
bit [15:12] :reserved (must be set to zero)
filter coefficient
bit [5:0] :
bit [7:6] :
data slicer
bit [7:0] :
binary sync slicer level is compared with binary data
(0
0
1
reserved (must be read don’t care)
0
1
0
1
number of detected horizontal sync pulses per frame / 4
sync is detected within horizontal window of HPLL
counter is latched with vertical sync
the register can be read at any time
binary soft slicer level is compared with ABS[data]
(–128 data +127)
reserved (must be set to zero)
0
1
high pass filter coefficient in 2’s complement
100000 = not allowed
100001 = –31
000000 =
011111 = +31
reserved (must be set to zero)
binary data slicer level is compared with ABS[data]
(–128
I
2
C-Registers VPX Slicer
data
vertical sync window enable
vertical sync window disable
vert. window
vert. retrace
field 2
field 1
= 2
= 702 for WST PAL
= 579 for WST NTSC or NABTS
= 506 for VPS or WSS
= 102 for CAPTION
= 627 for Antiope
= 183 for Time Code
phase inc = Freq
phase inc = Freq*(1+1/8) before framing code
phase inc = Freq*(1+1/16) after framing code
data
Sync Slicer
Bit Slicer
127)
11
0
* bitfreq / 20.25MHz
+127)
reset at line 624/524 (PAL/NTSC)
set at line 628/528 (PAL/NTSC)
reset at line 313/263 (PAL/NTSC)
set at line 624/524 (PAL/NTSC)
PRELIMINARY DATA SHEET
Default
64
0
16
702
1
0
7
64
Name
sync_slicer
sync_level
vsw
sync_stat
vwin
field
sync_cnt
soft_slicer
soft_level
ttx_freql
ttx_freqh
ttx_freq
ttx_phinc
filter
coeff
data_slicer
data_level
Micronas