vpx3224d ETC-unknow, vpx3224d Datasheet - Page 17

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

Micronas
PRELIMINARY DATA SHEET
2.6. Video Output Interface
Contrary to the component processing stage running at
a clock rate of 20.25 MHz, the output formatting stage
(Fig. 2–16) receives the video samples at a pixel trans-
port rate of 13.5 MHz. It supports 8 or 16-bit video for-
mats with separate or embedded reference signals, pro-
vides bus shuffling, and channels the output via one or
both 8-bit ports. Data transfer is synchronous to the in-
ternally generated 13.5 MHz pixel clock.
The format of the output data depends on three parame-
ters:
– the selected output format
– the number of active ports (A only, or both A and B)
– clock speed (single, double, half).
In 8-bit modes using only Port A for video data, Port B
can be used as programmable output.
Video
Samples
Reference
Signals
Fig. 2–16: Output format stage
Luminance
(Port A)
Chrominance
(Port B)
VACT
PIXCLK
LLC
Fig. 2–17: Detailed data output (single clock mode)
S YUV 4:2:2, separate syncs
S YUV 4:2:2, ITU-R656
S YUV 4:2:2, embedded reference codes (BStream)
16
8
8
Generation
Clock
8
8
Y
C
1
1
2.6.1. Output Formats
The VPX supports the YUV 4:2:2 video format only. Dur-
ing normal operation, all reference signals are output
separately. To provide a reduced video interface, the
VPX offers two possibilities for encoding timing refer-
ences into the video data stream: an ITU-R656 com-
pliant output format with embedded timing reference
headers and a second format with single timing control
codes in the video stream. The active output format can
be selected via FP-RAM 0x150 [format].
2.6.1.1. YUV 4:2:2 with Separate Syncs/ITU-R601
The default output format of the VPX is a synchronous
16-bit YUV 4:2:2 data stream with separate reference
signals. Port A is used for luminance and Port B for chro-
minance-information. Video data is compliant to ITU-
R601. Bit[1:0] of FP-RAM 0x150 has to be set to 00. Fig-
ure 2–17 shows the timing of the data ports and the
reference signals in this mode.
8
8
VPX 3225D, VPX 3224D
Y
C
n–1
n–1
Y
C
n
n
Port A
Port B
PIXCLK
LLC
LLC2
HREF
VREF
VACT
OE
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