vpx3224d ETC-unknow, vpx3224d Datasheet - Page 22

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

22
VPX 3225D, VPX 3224D
2.7.2. Half Clock Mode
For applications demanding a low bandwidth for the
transmission between video decoder and graphics con-
troller, the clock signal qualifying the output pixels
(PIXCLK) can be divided by 2. This mode is enabled by
setting Bit 5 of the FP-RAM 0x150 [halfclk]. Note that the
output format ITU-R601 must be selected. The timing of
the data and clock signals in this case is described in Fig-
ure 2–25.
If the half-clock mode is enabled, each second pulse of
PIXCLK is gated. PIXCLK can be used as a qualifier for
valid data. To ensure that the video data stream can be
spread, the selected number of valid output samples
should not exceed 400.
Luminance
(Port A)
Chrominance
(Port B)
VACT
PIXCLK
LLC
Fig. 2–23: Output timing in single clock mode
Video
(Port A)
VACT
PIXCLK
LLC
Fig. 2–24: Output timing in double clock mode
Luminance
(Port A)
Chrominance
(Port B)
VACT
PIXCLK
LLC
Fig. 2–25: Output timing in half clock mode
C
Y
1
1
Y
C
C
1
1
1
Y
1
C
Y
C
n–1
n–1
n–1
Y
n–1
Y
C
PRELIMINARY DATA SHEET
n
n
C
Y
C
n
n
n
Y
n
Micronas