vpx3224d ETC-unknow, vpx3224d Datasheet - Page 34

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

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VPX 3225D, VPX 3224D
2.13.2. Sliced VBI Data
The sliced data mode is enabled with bit[1] of the
FP-RAM 0x138 (vbimode). This mode uses the inte-
grated data slicer (available only on VPX 3225D) and
delivers decoded data samples to the output ports.
The data slicer provides data packets of a constant size
(filled with dummy bytes). The data packets have a de-
fault size of 64 bytes. To reduce the data rate for text sys-
tems with a smaller number of data bytes, the packet
size can be reduced via FP-RAM 0x139.
During lines within the VBI-window, specified by the user
settings in the corresponding Load-Table, the VPX inter-
nally multiplexes the data slicer packets onto the lumi-
nance and chrominance outputs. Since the values 0,
254, and 255 are protected in the 8-bit output modes
(ITU-R656, BStream), each slicer sample is separated
into two nibbles for transmission. Table 2–14 shows the
implemented data formats.
In each path, one nibble is transmitted twice. The LSB
is inverted for odd parity. This assures that the values 0
and 255 will not occur (for the detection of embedded
syncs). In the mode with embedded timing event codes,
chrominance data will be limited additionally. No signifi-
cant information will be lost since only Bit 0 and 1 will be
modified. Figure 2–38 shows the timing of data and ref-
erence signals in this mode.
Luminance
(Port A)
Chrominance
(Port B)
VACT
PIXCLK
LLC
Fig. 2–38: Timing during lines with sliced VBI-data (single clock mode)
D
D
1 (LSBs)
1 (MSBs)
Table 2–14: Splitting of sliced data to luminance and
chrominance output
The splitting described above can be disabled by setting
bit 6 in the ‘format_select’ register. In this case, the sliced
samples will be transmitted in the luminance path only.
To avoid modification of valid data, the limitation of lumi-
nance data in the 8-bit output modes should be sup-
pressed with bit 8 in the same register (note that lumi-
nance codes will not be protected).
Slicer
Data
Chroma
Output
Luma
Output
Word
MSB
S7
S7
S3
7
D
D
63 (LSBs)
63 (MSBs)
S6
S6
S2
6
S5
S5
S1
5
PRELIMINARY DATA SHEET
D
D
S4
S4
S0
4
Bit No.
64 (LSBs)
64 (MSBs)
S3
S7
S3
3
S2
S6
S2
2
S1
S5
S1
Micronas
1
LSB
S0
S4
S0
0