PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 10

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

9. BYTE 8: Byte Count Read back Register (1=Enable, 0=Disable)
10. BYTE 9: WATCHDOG Fall Back Register (1=Enable, 0=Disable)
11. BYTE 10: WATCHDOG TIMER Register (1=Enable, 0=Disable)
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Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDT ENB
Name
WDT<5>
WDT<4>
WDT<3>
WDT<2>
WDT<1>
WDT<0>
Pin#
Pin#
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Default
Default
Default
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register will determine the number of byte counts to be read back.
Watchdog Timer Unit
Bit[7:6]: 00 = 250 ms, 01 = 500ms, 10 = 1s, 11 = 4s
Initialization setting for Linear Programming Byte after Watch dog reset.
0= Byte 7 initialized to 0 after WD-Reset generated.
1= Byte 7 unchanged after WD-Reset generated.
Reserved
WDT Fall-back Frequency selection for FS3
WDT Fall-back Frequency selection for FS2
WDT Fall-back Frequency selection for FS1
WDT Fall-back Frequency selection for FS0
Watchdog Timer Enable Bit. 1=Enable, 0=Disable
0=Watch Dog falls back to hardware jumper setting frequency
1=Watch Dog falls back to fall back frequency setting in Byte 9.
Watchdog Time Interval Bit 5 (MSB)
Watchdog Time Interval Bit 4
Watchdog Time Interval Bit 3
Watchdog Time Interval Bit 2
Watchdog Time Interval Bit 1
Watchdog Time Interval Bit 0 (LSB)
Description
Description
Description
PRELIMINARY
PLL202-151
Rev 11/05/01 Page 10