PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 8

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

3. BYTE 2: PCI Clock Register (1=Enable, 0=Disable)
4. BYTE 3: AGP Clock Register (1=Enable, 0=Disable)
5. BYTE 4: REF Clock Register (1=Enable, 0=Disable)
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Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MULTSEL1
MULTSEL0
Pin#
Pin#
Pin#
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
18
17
15
14
12
11
46
21
56
20
21
8
7
6
1
-
-
-
-
-
Default
Default
Default
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
IREF Multiplier setting, bi t [0,7]
00= 4xIREF
01= 5xIREF
10= 6xIREF
11= 7xIREF
PCI5 (1=Active 0=Inactive)
PCI4 (1=Active 0=Inactive)
PCI3 (1=Active 0=Inactive)
PCI2 (1=Active 0=Inactive)
PCI1 (1=Active 0=Inactive)
PCI0 (1=Active 0=Inactive)
IREF Multiplier setting. See Bit 7.
Description
FBOUT (1=Active 0=Inactive)
24_48MHZ selection. 0=24Mhz, 1=48Mhz
REF1 double drive strength selection. 1=normal, 0=2X
REF1 (1=Active 0=Inactive)
AGP0_ZCLK double drive strength selection. 1=normal, 0=2X
AGP2 (1=Active 0=Inactive)
AGP1 (1=Active 0=Inactive)
AGP0 (1=Active 0=Inactive)
Description
Inverted Power-up latched FS3 value (Read only)
Inverted Power-up latched FS2 value (Read only)
Inverted Power-up latched FS1 value (Read only)
Inverted Power-up latched FS0 value (Read only)
48Mhz (1=Active 0=Inactive)
24_48Mhz (1=Active 0=Inactive)
PCI5 double drive strength selection. 1=normal, 0=2X
REF0 (1=Active 0=Inactive)
PRELIMINARY
PLL202-151
Rev 11/05/01 Page 8