PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 7

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

I2C CONTROL REGISTERS
1. BYTE 0: Functional and Frequency Select Clock Register (1=Enable, 0=Disable)
2. BYTE 1: CPU clock Register (1=Enable, 0=Disable)
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Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
Pin#
52,53
48,49
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
20
21
10
29
10
30
31
32
1
-
-
-
-
-
Default
Default
Power-up
FS3:FS0
Latched
value
0
0
1
0
1
1
1
1
1
1
1
1
Description
FS3
FS2
FS1
FS0
Frequency selection bit 1=Via I2C, 0=Via External jumper
Spread Spectrum modulation amplitude selection.
0= 0.3% (center)
1= 0.6% (center)
0=normal, 1= Spread Spectrum Enable
(Reserved).
Description
DDRC5/SDRAM11 (1=Active 0=Inactive)
PCI_F (1=Active 0=Inactive)
DDRT5/SDRAM10 (1=Active 0=Inactive)
DDRC4/SDRAM9 (1=Active 0=Inactive)
MULTSEL (IREF multiple) MODE Selection.
1= selection through hardware input pin 38
0= selection through I2C control by Byte2.bit[0,7]
DDRT4/SDRAM8 (1=Active 0=Inactive)
CPUT/CPU0D_T, CPUC/CPU0D_C (1=Active 0=Inactive)
CPU_CS_T, CPU_CS_C (1=Active 0=Inactive)
PRELIMINARY
PLL202-151
Rev 11/05/01 Page 7