PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 19

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

BUILT- IN WATCHDOG TIMER (WDT)
Watchdog timer is used to perform safe recovery if frequency switching causes system to enter into
“Hang-up” state within a reasonable period of time (or Watchdog time interval). While disabled, the
watchdog time interval can be programmed between 0 and 63 seconds with increment of 1 second by
setting the value of I2C.Byte10.Bit(5:0). Once Enabled, WDT has to be disabled within a period that is
shorter than the programmed watchdog interval; otherwise WDT will generate a 500ms low watchdog
reset pulse to provoke a system reset. After system restarts, the PLL202-151 will start from predefined
Fall-back Frequency (the value of I2C Byte9, bits(5:3)). If system for any reason fails again at Fall-back
Frequency, the internal hardware will then generate a watchdog reset to restart the system from the
value of external hardware jumper setting to ensure a safe recovery.
Example usage:
1. System power-up at CPU= 66.6MHz where external jumpers are used.
2A. Switch to target CPU=100.0MHz frequency with following I2C register setting:
2B. Switch to target CPU=103Mhz within the same timing Group
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The fall-back frequency is set to the same l ocation as that of FSEL since
frequency switching between different timing groups will cause system to hang
up. After WD timer expired or 15 seconds, the system will restart properly at
target 100.0MHz if CPU is capable; otherwise WDT will perform another reset
action to restart the system from 66.8 Mhz
The fall-back frequency is recommended to set at the most safe and comfortable
level to ensure a successful reboot such as 100 if system is unable to switch to
103Mhz.
Sign M 6 M 5 M 4 M 3 M 2 M 1 M 0
E N B
F B 4 F B 3 F B 2 F B 1 F B 0
7
7
7
0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1
0 0 0 0 1 0 0 0
6
6
6
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
T 5
5
5
5
T 4
4
4
4
T 3
3
3
3
T 2
2
2
2
T 1
1
1
1
T 0
0
0
0
M =0
WD-Timer = 15s
FBSEL
PRELIMINARY
Setting in I2C.BYTE7
Setting in I2C.BYTE8
Setting in I2C.BYTE6
PLL202-151
Rev 11/05/01 Page 19