PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 12

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

TABLE 1: Output Signals SKEW Programming Summary:
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Bit<2:0>
Bit<3:0>
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
111
110
101
100
011
010
001
000
+1,875ps
+1,750ps
+1,625ps
+1,500ps
+1,375ps
+1,250ps
+1,125ps
+1,000ps
Default
Default
+320ps
+240ps
+160ps
+875ps
+750ps
+625ps
+500ps
+375ps
+250ps
+125ps
-160ps
-240ps
+80ps
-80ps
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
AccuSkew Setting I
Skew Setting IV
( 80ps/step)
(125ps/step)
Setting applies to the
following outputs:
1. CPU-Host
2. CPU-CS
Setting applies to the
following outputs
1. FBOUT (VIA mode)
3. DDR/SDRAM (non-
VIA)
Default
+640ps
+480ps
+320ps
+160ps
-160ps
-320ps
-480ps
AccuSkew Setting II
( 160ps/step)
Setting applies to the
following outputs:
1. AGP0_ZCLK
2. AGP1, AGP2
3. All PCI
PRELIMINARY
Default
+875ps
+750ps
+625ps
+500ps
+375ps
+250ps
+125ps
PLL202-151
Skew Setting III
(125ps/step)
Setting applies to the
following outputs:
1.DDR/SDRAM
(Via mode)
Rev 11/05/01 Page 12