EPM570 Altera, EPM570 Datasheet - Page 12

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

Logic Array Blocks
Figure 2–4. DirectLink Connection
2–6
MAX II Device Handbook, Volume 1
DirectLink interconnect from
left LAB or IOE output
interconnect
DirectLink
to left
Interconnect
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include two clocks, two clock enables, two
asynchronous clears, a synchronous clear, an asynchronous preset/load,
a synchronous load, and add/subtract control signals, providing a
maximum of 10 control signals at a time. Although synchronous load and
clear signals are generally used when implementing counters, they can
also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal also uses labclkena1. If the
LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal turns off the
LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. The asynchronous load acts as a preset when the
asynchronous load data input is tied high.
Local
Core Version a.b.c variable
Logic Element
LE0
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LAB
DirectLink
interconnect
to right
DirectLink interconnect from
right LAB or IOE output
Altera Corporation
December 2004