EPM570 Altera, EPM570 Datasheet - Page 48

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

IEEE Std. 1149.1 (JTAG) Boundary Scan Support
3–2
MAX II Device Handbook, Volume 1
Notes to
(1)
(2)
HIGHZ
CLAMP
USER0
USER1
IEEE 1532 instructions
Table 3–1. MAX II JTAG Instructions (Part 2 of 2)
JTAG Instruction
HIGHZ, CLAMP, and EXTEST instructions do not disable weak pull-up resistors or bus hold features.
These instructions are shown in the 1532 BSDL files, which will be posted on the Altera
www.altera.com when they are available.
(1)
(1)
Table
3–1:
Instruction Code
00 0000 1011
00 0000 1010
00 0000 1100
00 0000 1110
(2)
Core Version a.b.c variable
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation, while tri-stating all of the I/O
pins.
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation, while holding I/O pins to a
state defined by the data in the boundary-scan register.
This instruction allows the user to define their own scan chain
between TDI and TDO in the MAX II logic array. This
instruction is also used for custom logic and JTAG interfaces.
This instruction allows the user to define their own scan chain
between TDI and TDO in the MAX II logic array. This
instruction is also used for custom logic and JTAG interfaces.
IEEE 1532 ISC instructions used when programming a MAX II
device via the JTAG port.
Description
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Altera Corporation
December 2004