EPM570 Altera, EPM570 Datasheet - Page 47

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

IEEE Std. 1149.1
(JTAG) Boundary
Scan Support
Altera Corporation
December 2004
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
MII51003-1.2
Table 3–1. MAX II JTAG Instructions (Part 1 of 2)
JTAG Instruction
(1)
Instruction Code
00 0000 0101
00 0000 1111
11 1111 1111
00 0000 0111
00 0000 0110
All MAX
scan test (BST) circuitry that complies with the IEEE Std. 1149.1-2001
specification. JTAG boundary-scan testing can only be performed at any
time after V
t
port for in-system programming together with either the Quartus
software or hardware using Programming Object Files (.pof), Jam
Standard Test and Programming Language (STAPL) Files (.jam) or Jam
Byte-Code Files (.jbc).
The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The
supported voltage level and standard is determined by the V
bank where it resides. The dedicated JTAG pins reside in Bank 1 of all
MAX II devices.
MAX II devices support the JTAG instructions shown in
CONFIG
amount of time has passed. MAX II devices can also use the JTAG
®
Core Version a.b.c variable
II devices provide Joint Test Action Group (JTAG) boundary-
CCINT
Chapter 3. JTAG & In-System
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation, and permits an
initial data pattern to be output at the device pins.
Allows the external circuitry and board-level interconnects to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation.
Selects the 32-bit USERCODE register and places it between
the TDI and TDO pins, allowing the USERCODE to be serially
shifted out of TDO. This register defaults to all 1’s if not
specified in the Quartus II software.
Selects the IDCODE register and places it between TDI and
TDO, allowing the IDCODE to be serially shifted out of TDO.
and all V
CCIO
banks have been fully powered and a
Description
Programmability
Table
CCIO
Preliminary
3–1.
®
of the
TM
II
3–1