EPM570 Altera, EPM570 Datasheet - Page 4

no-image

EPM570

Manufacturer Part Number
EPM570
Description
MAX II Device Family
Manufacturer
Altera
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM570F-256C5N
Manufacturer:
ALTERA
Quantity:
462
Part Number:
EPM570F100
Manufacturer:
ALTERA
0
Part Number:
EPM570F100A5N
Manufacturer:
ALTERA
0
Part Number:
EPM570F100C
Manufacturer:
ALTERA
0
Part Number:
EPM570F100C4N
Manufacturer:
ALTERA
Quantity:
12 388
Part Number:
EPM570F100C4N
Manufacturer:
ALTERA
Quantity:
325
Part Number:
EPM570F100C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPM570F100C4N
Manufacturer:
ALTERA
0
Part Number:
EPM570F100C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM570F100C5N
Manufacturer:
NICHIA
Quantity:
1 001
Part Number:
EPM570F100C5N
Manufacturer:
ALTERA
Quantity:
490
Part Number:
EPM570F100C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM570F100C5N
0
Features
Features
1–2
MAX II Device Handbook, Volume 1
Notes to
(1)
(2)
LEs
Typical Equivalent
Macrocells
Equivalent Macrocell
Range
UFM Size (bits)
Maximum User I/O pins
t
f
t
t
PD1
CNT
SU
CO
Table 1–1. MAX II Device Features
(ns)
(ns)
(ns)
(MHz)
t
combinational logic implemented in a single LUT and LAB that is adjacent to the output pin.
The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay
will run faster than this number.
PD1
Feature
(1)
represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and
Table
(2)
1–1:
Table 1–1
128 to 240
EPM240
8,192
240
192
304
4.7
2.0
4.4
80
Low-cost, low-power CPLD
Instant-on, non-volatile architecture
Standby current as low as 2 mA
Provides fast propagation delay and clock-to-output times
Provides four global clocks with two clocks available per logic array
block (LAB)
UFM block up to 8 Kbits for non-volatile storage
MultiVolt core enabling external supply voltages to the device of
either 3.3 V/2.5 V or 1.8 V
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic
levels
Bus-friendly architecture including programmable slew rate, drive
strength, bus-hold, and programmable pull-up resistors
Schmitt triggers enabling noise tolerant inputs (programmable per
pin)
Fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for
3.3-V operation at 33 MHz
Supports hot-socketing
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
shows MAX II device features.
Core Version a.b.c variable
240 to 570
EPM570
8,192
570
440
160
304
5.5
1.8
4.5
570 to 1,270
EPM1270
1,270
8,192
980
212
304
6.3
1.8
4.6
Altera Corporation
1,270 to 2,210
December 2004
EPM2210
2,210
1,700
8,192
272
304
7.1
1.8
4.7

Related parts for EPM570