EPM570 Altera, EPM570 Datasheet - Page 73

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

Altera Corporation
December 2004
Notes to
(1)
(2)
(3)
(4)
UFM
t
t
t
t
t
Resource
LUT
CLR
PRE
SU
H
Table 5–14. MAX II Device Performance (Part 2 of 2)
Table 5–15. LE Internal Timing Microparameters (Part 1 of 2)
Symbol
Used
This design is a binary loadable up counter.
This design is configured for read only operation in Extended mode. Read and write ability increases the number
of LEs used.
This design is configured for read-only operation. Read and write ability increases the number of LEs used.
This design is asynchronous.
Table
LE combinational
LUT delay
LE register clear
delay
LE register preset
delay
LE register setup
time before clock
LE register hold time
after clock
512 x 16
512 x 16
512 x 8
Function
Design
Size &
5–14:
Parameter
f
None
SPI
Parallel
Mode
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density.
MAX II device internal timing microparameters for logic elements (LEs),
input/output elements (IOEs), UFM structures, and MultiTrack
interconnects.
For more explanations and descriptions on each internal timing
microparameters symbol, refer to the chapter on Understanding Timing in
MAX II Devices.
(2)
(3)
-3 Speed Grade
Min
243
243
113
0
Core Version a.b.c variable
Resources Used
LEs
37
73
3
Max
583
Blocks
UFM
1
1
1
-4 Speed Grade
Min
315
315
146
0
-3 Speed
Tables 5–15
Grade
10.0
9.8
(4)
Max
757
MAX II Device Handbook, Volume 1
Performance
-4 Speed
DC & Switching Characteristics
Grade
through
10.0
9.8
(4)
-5 Speed Grade
Min
388
388
180
0
5–22
-5 Speed
Grade
10.0
9.7
(4)
Max
932
describe the
TM
MHz
MHz
MHz
Unit
Unit
ps
ps
ps
ps
ps
5–11