EPM570 Altera, EPM570 Datasheet - Page 78

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

Timing Model & Specifications
5–16
MAX II Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
PPMX
AE
EB
BE
EPMX
DCO
OE
RA
OSCS
OSCH
Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 2)
Symbol
Maximum length of
busy pulse during a
program
Minimum erase
signal to address
clock hold time
Maximum delay
between the erase
rising edge to the
UFM busy signal
rising edge
Minimum delay
allowed from the
UFM busy signal
going low to erase
signal going low
Maximum length of
busy pulse during an
erase
Delay from data
register clock to data
register output
Delay from data
register clock to data
register output
Maximum read
access time
Maximum delay
between the
OSC_ENA rising
edge to the
erase/program
signal rising edge
Minimum delay
allowed from the
erase/program
signal going low to
OSC_ENA signal
going low
Parameter
Figures 5–2
for UFM block timing parameters shown in
-3 Speed Grade
Min
136
350
350
Core Version a.b.c variable
20
0
through
Max
100
960
500
65
5
5–4
show the read, program, and erase waveforms
-4 Speed Grade
Min
136
350
350
20
0
Max
100
960
500
65
5
Table
-5 Speed Grade
Min
136
350
350
20
0
5–21.
Altera Corporation
Max
100
960
500
December 2004
65
5
Unit
ms
µs
ns
ns
ns
ns
ns
ns
ns
ns