MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 218

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

11
11.4.3
In the extended addressing mode, the effective address of the argument is contained in two bytes
following the opcode byte. These are three-byte instructions (or four-byte instructions if a prebyte
is required). One or two bytes are needed for the opcode and two for the effective address.
11.4.4
In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to
the value contained in an index register (IX or IY) — the sum is the effective address. This
addressing mode allows referencing any memory location in the 64Kbyte address space. These
are two- to five-byte instructions, depending on whether or not a prebyte is required.
11.4.5
In the inherent addressing mode, all the information necessary to execute the instruction is
contained in the opcode. Operations that use only the index registers or accumulators, as well as
control instructions with no arguments, are included in this addressing mode. These are one or
two-byte instructions.
11.4.6
The relative addressing mode is used only for branch instructions. If the branch condition is true,
an 8-bit signed offset included in the instruction is added to the contents of the program counter
to form the effective branch address. Otherwise, control proceeds to the next instruction. These
are usually two-byte instructions.
11.5
Refer to Table 11-2, which shows all the M68HC11 instructions in all possible addressing modes.
For each instruction, the table shows the operand construction, the number of machine code
bytes, and execution time in CPU E clock cycles.
MOTOROLA
11-8
Extended (EXT)
Indexed (IND, X; IND, Y)
Inherent (INH)
Relative (REL)
Instruction set
CPU CORE AND INSTRUCTION SET
MC68HC11PH8
TPG