MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 97

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

for the remainder of that message. When the next message begins, its first frame will have the
MSB set which will automatically clear the RWU bit and indicate that this is an addressing frame.
This frame is always the first frame received after wake-up because the RWU bit is cleared before
the stop bit for the first frame is received. This method of wake-up allows messages to include idle
times, however, there is a loss in efficiency due to the extra bit time required for the address bit in
each frame.
5.5
Four error conditions can occur during SCI operation. These error conditions are: serial data
register overrun, received bit noise, framing, and parity error. Four bits (OR, NF, FE, and PF) in
serial communications status register 1 (SCSR1) indicate if one of these error conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be transferred from the receive
shift register to the serial data registers (SCDRH/SCDRL) and the registers are already full (RDRF
bit is set). When an overrun error occurs, the data that caused the overrun is lost and the data that
was already in serial data registers is not disturbed. The OR is cleared when the SCSR is read
(with OR set), followed by a read of the SCI data registers.
The noise flag (NF) bit is set if there is noise on any of the received bits, including the start and
stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is cleared when the SCSR is
read (with FE equal to one) followed by a read of the SCI data registers.
When no stop bit is detected in the received data character, the framing error (FE) bit is set. FE is
set at the same time as the RDRF. If the byte received causes both framing and overrun errors,
the processor only recognizes the overrun error. The framing error flag inhibits further transfer of
data into the SCI data registers until it is cleared. The FE bit is cleared when the SCSR is read
(with FE equal to one) followed by a read of the SCI data registers.
The parity error flag (PF) is set if received data has incorrect parity. The flag is cleared by a read
of SCSR1 with PE set, followed by a read of SCDR.
5.6
There are eight addressable registers in the SCI. SCBDH, SCBDL, SCCR1, and SCCR2 are
control registers. The contents of these registers control functions and indicate conditions within
the SCI. The status registers SCSR1 and SCSR2 contain bits that indicate certain conditions
within the SCI. SCDRH and SCDRL are SCI data registers. These double buffered registers are
used for the transmission and reception of data, and are used to form the 9-bit data word for the
SCI. If the SCI is being used with 7 or 8-bit data, only SCDRL needs to be accessed. Note that if
9-bit data format is used, the upper register should be written first to ensure that it is transferred
to the transmitter shift register with the lower register.
MC68HC11PH8
SCI error detection
SCI registers
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
TPG
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