MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 45

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

LCDCK — LCD frequency clock select
When the PLL clock generation circuit is not used (VDDSYN = 0), setting LCDCK selects the
ST4XCK clock divided by 2
generation circuit is used (VDDSYN = 1), setting LCDCK selects the output of the 8-bit modulus
timer A divided by 2
LCDE — LCD function enable
The LCDE bit can be written only once (the first write to this register after reset will prevent later
updates of this bit). When enabled, this function will force PG6 into output mode. This output will
be the backplane signal (LCDBP) for the four LCD segments. The four port B pins (PB[7:4]) used
to drive the LCD segments will also be forced into output mode. If enabled in expanded modes,
PB[7:4] will operate as LCD outputs, while PB3 to PB0 output the address lines to access external
resources. To avoid conflicts caused by the LCDE bit being set accidentally by program error, it is
recommended that the LCDE bit be written to zero if the LCD function is not required.
MC68HC11PH8
1 (set)
0 (clear) –
1 (set)
0 (clear) –
–
–
3
The clock source of the real time interrupt (RTI) toggles LCDBP.
8-bit modulus timer A underflow (CLK64) toggles LCDBP.
(CLK64/2
LCD function enabled.
LCD function disabled.
18
3
) as the LCD clock source. Refer to Section 8.
as the LCD clock source. Conversely, when the PLL clock
PIN DESCRIPTIONS
MOTOROLA
TPG
2-19
2