MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 65

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

PH8.DS03/Modes+mem
STRCH — Stretch external accesses
When this bit is set, off-chip accesses of selected addresses are extended by one E clock cycle
to allow access to slow peripherals. The E clock stretches externally, but the internal clocks are
not affected, so that timers and serial systems are not corrupted. The state of the STRX
the INIT2 register) and the ROMAD bit (in the CONFIG register) determines which address range
is affected. See Section 3.3.2.3.
Note:
To use this feature, ROMON must be set on reset so that the device starts with internal ROM
included in the memory map. STRCH should then be set.
Setting STRX means that all external accesses are stretched. If required (and allowed), ROMON
can then be cleared so that internal ROM is not present in the memory map (see Section 3.4.3).
If STRX is cleared, then external accesses from $0000 to $1FFF (ROMAD set) or from $C000 to
$DFFF (ROMAD cleared) are stretched.
STRCH has no effect in single chip and boot modes.
IRVNE — Internal read visibility/not E
IRVNE can be written once in any user mode. In expanded modes, IRVNE determines whether
IRV is on or off (but has no meaning in user expanded secure mode, as IRV must be disabled). In
special test mode, IRVNE is reset to one. In normal modes, IRVNE is reset to zero.
In single chip modes this bit determines whether the E clock drives out from the chip.
Refer to the following table for a summary of the operation immediately following reset.
MC68HC11PH8
†
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
The STRX bit is not present on early versions of the MC68HC711PH8; on those devices,
setting STRCH means that external accesses either from $0000 to $FFFF or from $C000 to
$DFFF are stretched, depending on the state of ROMAD. Contact your local Motorola Sales
Representative for further information.
STRCH is cleared on reset; therefore a program cannot execute out of reset in a slow
external ROM.
–
–
–
Off-chip accesses are selectively extended by one E clock cycle.
Normal operation.
Data from internal reads is driven out of the external data bus.
No visibility of internal reads on external bus.
E pin is driven low.
E clock is driven out from the chip.
OPERATING MODES AND ON-CHIP MEMORY
—this line does not form part of the document—
[DS97 v 4.1] 08/Apr/97@13:55
MOTOROLA
†
bit (in
TPG
3-19
10
12
13
14
15
11
1
2
3
4
5
6
7
8
9