EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 32

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

2–26
Arria GX Device Handbook, Volume 1
f
For more information about transceiver clocking in all supported functional modes,
refer to the
PLD Clock Utilization by Transceiver Blocks
Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional clock
(RCLK) lines that are used to route the transceiver clocks. The following transceiver
clocks use the available global and regional clock resources:
■
■
■
■
■
■
Figure 2–23
GX devices.
Figure 2–23. Global Clock Resources in Arria GX Devices
pll_inclk (if driven from an FPGA input pin)
rx_cruclk (if driven from an FPGA input pin)
tx_clkout/coreclkout (CMU low-speed parallel clock forwarded to the PLD)
Recovered clock from each channel (rx_clkout) in non-rate matcher mode
Calibration clock (cal_blk_clk)
Fixed clock (fixedclk used for receiver detect circuitry in PCI Express [PIPE]
mode only)
Arria GX Transceiver Architecture
and
CLK[3..0]
Figure 2–24
7
1
2
8
GCLK[3..0]
show the available GCLK and RCLK resources in Arria
GCLK[15..12]
CLK[15..12]
GCLK[4..7]
CLK[7..4]
11 5
12 6
chapter.
GCLK[11..8]
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Transceiver
Transceiver
Arria GX
Arria GX
Block
Block
Transceivers