EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 47

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–37. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
Shared Arithmetic Chain
© December 2009 Altera Corporation
3-Bit Add Example
implemented in adders.
implemented in LUTs.
+
2nd stage add is
1st stage add is
1 1 0 1
1 1 0
+
Binary Add
1 1 0
1 0 1
0 1 0
0 0 1
Adder trees are used in many different applications. For example, the summation of
partial products in a logic-based multiplier can be implemented in a tree structure.
Another example is a correlator function that can use a large adder tree to sum filtered
data samples in a given time frame to recover or to de-spread data which was
transmitted utilizing spread spectrum technology. An example of a three-bit add
operation utilizing the shared arithmetic mode is shown in
sum (S[2..0]) and the partial carry (C[2..0]) is obtained using LUTs, while the
result (R[2..0]) is computed using dedicated adders.
In addition to dedicated carry chain routing, the shared arithmetic chain available in
shared arithmetic mode allows the ALM to implement a three-input add, which
significantly reduces the resources necessary to implement large adder trees or
correlator functions. Shared arithmetic chains can begin in either the first or fifth ALM
in a LAB. The Quartus II Compiler automatically links LABs to create shared
arithmetic chains longer than 16 (eight ALMs in arithmetic or shared arithmetic
mode). For enhanced fitting, a long shared arithmetic chain runs vertically allowing
fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic
chain can continue as far as a full column. Similar to carry chains, shared arithmetic
+
R3 R2 R1 R0
C2 C1 C0
+
+
Equivalents
Decimal
X2 X1 X0
S2 S1 S0
2 x 6
Y2 Y1 Y0
Z2 Z1 Z0
+
13
6
5
2
1
X0
Y0
X1
Y1
X2
Y2
Z0
Z1
Z2
ALM Implementation
ALM 1
ALM 2
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
S0
C0
S1
C1
S2
C2
shared_arith_in = '0'
'0'
carry_in = '0'
Arria GX Device Handbook, Volume 1
Figure
2–37. The partial
R0
R1
R2
R3
2–41