EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 78

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

2–72
Enhanced and Fast PLLs
Table 2–17. Arria GX Device PLL Availability
Table 2–18. Arria GX PLL Features (Part 1 of 2)
Arria GX Device Handbook, Volume 1
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
Notes to
(1) The global or regional clocks in a fast PLL's transceiver block can drive the fast PLL input. A pin or other PLL must drive the global or regional
(2) EP1AGX20C, EP1AGX35C/D, EP1AGX50C and EP1AGX60C/D devices only have two fast PLLs (PLLs 1 and 2), but the connectivity from these
(3) PLLs 3, 4, 9, and 10 are not available in Arria GX devices.
(4) 4 or 8 PLLs are available depending on C or D device and the package option.
(5) 4or 8 PLLs are available depending on C, D, or E device option.
Clock multiplication and division
Phase shift
Clock switchover
PLL reconfiguration
Reconfigurable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
source. The source cannot be driven by internally generated logic before driving the fast PLL.
two PLLs to the global and regional clock networks remains the same as shown in this table.
Device
Table
(5)
(4)
2–17:
Feature
Arria GX devices provide robust clock management and synthesis using up to four
enhanced PLLs and four fast PLLs. These PLLs increase performance and provide
advanced clock interfacing and clock frequency synthesis. With features such as clock
switchover, spread spectrum clocking, reconfigurable bandwidth, phase control, and
reconfigurable phase shifting, the Arria GX device’s enhanced PLLs provide you with
complete control of your clocks and system timing. The fast PLLs provide general
purpose clocking with multiplication and phase shifting as well as high-speed
outputs for high-speed differential I/O support. Enhanced and fast PLLs work
together with the Arria GX high-speed I/O and advanced clock architecture to
provide significant improvements in system performance and bandwidth.
The Quartus II software enables the PLLs and their features without requiring any
external devices.
type.
Table 2–18
v
v
v
v
v
1
v
v
v
v
v
2
lists the enhanced PLL and fast PLL features in Arria GX devices.
3
—
—
—
—
—
(3)
Down to 125-ps increments (3),
Table 2–17
Three differential/six single-ended
m/(n × post-scale counter)
(Note
4
—
—
—
—
—
Fast PLLs
(3)
1),
Enhanced PLL
(2)
lists the PLLs available for each Arria GX device and their
v
v
v
—
—
7
v
v
v
v
v
6
—
—
v
v
v
8
(1)
9
—
—
—
—
—
(4)
(3)
10
—
—
—
—
—
Down to 125-ps increments (3),
(3)
m/(n × post-scale counter)
© December 2009 Altera Corporation
v
v
v
v
v
5
Chapter 2: Arria GX Architecture
Fast PLL
Enhanced PLLs
v
(6)
v
v
v
—
v
v
v
v
v
4
6
(5)
PLLs and Clock Networks
11
—
—
v
v
v
(2)
(4)
v
v
v
12
—
—