EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 55

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Chapter 2: Arria GX Architecture
TriMatrix Memory
Table 2–11. TriMatrix Memory Features (Part 2 of 2)
M512 RAM Block
© December 2009 Altera Corporation
ROM
FIFO buffer
Pack mode
Byte enable
Address clock enable
Parity bits
Mixed clock mode
Memory initialization file (.mif)
Simple dual-port memory mixed width support
True dual-port memory mixed width support
Power-up conditions
Register clears
Mixed-port read-during-write
Configurations
Memory Feature
TriMatrix memory provides three different memory sizes for efficient application
support. The Quartus II software automatically partitions the user-defined memory
into the embedded memory blocks using the most efficient size combinations. You can
also manually assign the memory to a specific block size or a mixture of block sizes.
The M512 RAM block is a simple dual-port memory block and is useful for
implementing small FIFO buffers, DSP, and clock domain transfer applications. Each
block contains 576 RAM bits (including parity bits). M512 RAM blocks can be
configured in the following modes:
■
■
■
■
■
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
Unknown output/old
M512 RAM Block
Output registers
Outputs cleared
(32 × 18 Bits)
512 × 1
256 × 2
128 × 4
32 × 16
32 × 18
64 × 8
64 × 9
data
v
v
—
v
—
v
v
v
v
—
Unknown output/old
M4K RAM Block
Output registers
Outputs cleared
(128 × 36 Bits)
256 × 16
256 × 18
128 × 32
128 × 36
512 × 8
512 × 9
4K × 1
2K × 2
1K × 4
data
v
v
v
v
v
v
v
v
v
v
Arria GX Device Handbook, Volume 1
Outputs unknown
Unknown output
Output registers
(4K × 144 Bits)
M-RAM Block
32K × 16
32K × 18
16K × 32
16K × 36
4K × 128
4K × 144
64K × 8
64K × 9
8K × 64
8K × 72
v
v
v
v
v
v
v
v
—
—
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