EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 8

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

2–2
Figure 2–2. Arria GX Transceiver Channel Block Diagram
Notes to
(1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA.
(2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, or 20.
Arria GX Device Handbook, Volume 1
n = 8 or 10.
Figure
Reference
Reference
PMA Analog Section
Clock
Clock
2–2:
Deserializer
Transmitter
Serializer
Recovery
Receiver
Clock
Unit
PLL
PLL
Figure 2–1
into four channels.
Figure 2–1. Transceiver Block
Each transceiver block has:
■
■
■
■
Figure 2–2
(1)
(1)
n
n
Four transceiver channels with dedicated physical coding sublayer (PCS) and
physical media attachment (PMA) circuitry
One transmitter PLL that takes in a reference clock and generates high-speed serial
clock depending on the functional mode
Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from
the received serial data stream
State machines and other logic to implement special features required to support
each protocol
PCS Digital Section
Aligner
Word
shows a high-level diagram of the transceiver block architecture divided
shows functional blocks that make up a transceiver channel.
Deskew
Logic Array
XAUI
Lane
Arria GX
Encoder
8B/10B
Matcher
Rate
Transceiver Block
Decoder
8B/10B
(PLLs, State Machines,
Serializer
Supporting Blocks
Byte
Programming)
Channel 1
Channel 0
Channel 2
Channel 3
Deserializer
Byte
© December 2009 Altera Corporation
Compensation
FIFO Buffer
Phase
RX1
TX1
RX0
TX0
REFCLK_1
REFCLK_0
RX2
TX2
RX3
TX3
Chapter 2: Arria GX Architecture
Compensation
FIFO Buffer
Phase
FPGA Fabric
m
(2)
m
(2)
Transceivers