EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 50

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

2–44
MultiTrack Interconnect
Arria GX Device Handbook, Volume 1
In addition to the clear and load/preset ports, Arria GX devices provide a
device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set
before compilation in the Quartus II software controls this pin. This device-wide reset
overrides all other control signals.
In Arria GX architecture, the MultiTrack interconnect structure with DirectDrive
technology provides connections between ALMs, TriMatrix memory, DSP blocks, and
device I/O pins. The MultiTrack interconnect consists of continuous,
performance-optimized routing lines of different lengths and speeds used for inter-
and intra-design block connectivity. The Quartus II Compiler automatically places
critical design paths on faster interconnects to improve design performance.
DirectDrive technology is a deterministic routing technology that ensures identical
routing resource usage for any function regardless of placement in the device. The
MultiTrack interconnect and DirectDrive technology simplify the integration stage of
block-based designing by eliminating the re-optimization cycles that typically follow
design changes and additions.
The MultiTrack interconnect consists of row and column interconnects that span fixed
distances. A routing structure with fixed length resources for all devices allows
predictable and repeatable performance when migrating through different device
densities. Dedicated row interconnects route signals to and from LABs, DSP blocks,
and TriMatrix memory in the same row.
These row resources include:
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■
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The direct link interconnect allows a LAB, DSP block, or TriMatrix memory block to
drive into the local interconnect of its left and right neighbors and then back into
itself, providing fast communication between adjacent LABs and/or blocks without
using row interconnect resources.
The R4 interconnects span four LABs, three LABs and one M512 RAM block, two
LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of
a source LAB. These resources are used for fast row connections in a four-LAB region.
Every LAB has its own set of R4 interconnects to drive either left or right.
shows R4 interconnect connections from a LAB.
R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row
IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4
interconnect. For R4 interconnects that drive to the right, the primary LAB and right
neighbor can drive onto the interconnect. For R4 interconnects that drive to the left,
the primary LAB and its left neighbor can drive onto the interconnect. R4
interconnects can drive other R4 interconnects to extend the range of LABs they can
drive. R4 interconnects can also drive C4 and C16 interconnects for connections from
one row to another. Additionally, R4 interconnects can drive R24 interconnects.
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
R24 row interconnects for high-speed access across the length of the device
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
MultiTrack Interconnect
Figure 2–39