CY8C36_10 CYPRESS [Cypress Semiconductor], CY8C36_10 Datasheet - Page 21

• Manufacturer Part Number: CY8C36_10
• Manufacturer: CYPRESS [Cypress Semiconductor]

5.6.3.1 xdata Space
The 8051 xdata space is 24-bit, or 16 MB in size. The majority of
this space is not “external”—it is used by on-chip components.
See
accessed using the EMIF. See
page 18.
Table 5-3. XDATA Data Address Map
Document Number: 001-53413 Rev. *I
0×00 0000 – 0×00 1FFF
0×00 4000 – 0×00 42FF
0×00 4300 – 0×00 43FF
0×00 4400 – 0×00 44FF
0×00 4500 – 0×00 45FF
0×00 4700 – 0×00 47FF
0×00 4900 – 0×00 49FF
0×00 4E00 – 0×00 4EFF
0×00 4F00 – 0×00 4FFF
0×00 5000 – 0×00 51FF
0×00 5400 – 0×00 54FF
0×00 5800 – 0×00 5FFF
0×00 6000 – 0×00 60FF
0×00 6400 – 0×00 6FFF
0×00 7000 – 0×00 7FFF
0×00 8000 – 0×00 8FFF
0×00 A000 – 0×00 A400
0×00 C000 – 0×00 C800
0×01 0000 – 0×01 FFFF
0×05 0220 – 0×05 02F0
0×08 0000 – 0×08 1FFF
0×80 0000 – 0×FF FFFF
Table
Address Range
5-3. External, that is, off-chip, memory can be
SRAM
Clocking, PLLs, and oscillators
Power management
Interrupt controller
Ports interrupt control
Flash programming interface
I
Decimator
Fixed timer/counter/PWMs
I/O ports control
External Memory Interface
(EMIF) control registers
Analog Subsystem interface
USB controller
UDB configuration
PHUB configuration
EEPROM
CAN
Digital Filter Block
Digital Interconnect
configuration
Debug controller
flash ECC bytes
External Memory Interface
External Memory Interface
2
C controller
Purpose
PRELIMINARY
on
6. System Integration
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 66 MHz clock, accurate to ±1% over voltage and
temperature. Additional internal and external clock sources allow
each design to optimize accuracy, power, and cost. All of the
system clock sources can be used to generate other clock
frequencies in the 16-bit clock dividers and UDBs for anything
the user wants, for example a UART baud rate generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows you to build clocking
systems with minimal input. You can specify desired clock
frequencies and accuracies, and the software locates or builds a
clock that meets the required specifications. This is possible
because of the programmability inherent PSoC.
Key features of the clocking system include:
Seven general purpose clock sources
IMO has a USB mode that auto locks to the USB bus clock
requiring no external crystal for USB. (USB equipped parts only)
Independently sourced clock in all clock dividers
Eight 16-bit clock dividers for the digital system
Four 16-bit clock dividers for the analog system
Dedicated 16-bit divider for the bus clock
Dedicated 4-bit divider for the CPU clock
Automatic clock configuration in PSoC Creator
PSoC
3- to 62-MHz IMO, ±1% at 3 MHz
4- to 33-MHz external crystal oscillator (MHzECO)
Clock doubler provides a doubled clock frequency output for
the USB block, see
DSI signal from an external I/O pin or other logic
24- to 67-MHz fractional PLL sourced from IMO, MHzECO,
or DSI
Clock doubler
1-kHz, 33-kHz, 100-kHz ILO for WDT and sleep timer
32.768-kHz external crystal oscillator (kHzECO) for RTC
®
3: CY8C36 Family Datasheet
USB Clock Domain
on page 24.
Page 21 of 112
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