CY8C36_10 CYPRESS [Cypress Semiconductor], CY8C36_10 Datasheet - Page 7

• Manufacturer Part Number: CY8C36_10
• Manufacturer: CYPRESS [Cypress Semiconductor]

Notes
Document Number: 001-53413 Rev. *I
8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
9. This feature on select devices only. See
10. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
(configurable XRES, GPIO) P1[2]
(TCK, SWDCK, GPIO) P1[1]
(TMS, SWDIO, GPIO) P1[0]
(TDO, SWV, GPIO) P1[3]
(I2C0: SDA, SIO) P12[5]
(I2C0: SCL, SIO) P12[4]
(nTRST, GPIO) P1[5]
(TDI, GPIO) P1[4]
Ordering Information
(GPIO) P2[6]
(GPIO) P2[7]
Vboost
Vddio1
XRES
Vssb
Vssd
Vbat
Ind
PRELIMINARY
Figure 2-3. 68-pin QFN Part Pinout
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
on page 100 for details.
Lines show Vddio
to I/O supply
association
(Top View)
QFN
PSoC
®
[10]
3: CY8C36 Family Datasheet
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
P3[7] (GPIO, OpAmp3out)
P3[6] (GPIO, OpAmp1out)
Vddio3
[9]
[9]
Page 7 of 112
[+] Feedback