CY8C36_10 CYPRESS [Cypress Semiconductor], CY8C36_10 Datasheet - Page 49

• Manufacturer Part Number: CY8C36_10
• Manufacturer: CYPRESS [Cypress Semiconductor]

Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in CY8C36,
four in the left half (abusl [0:3]) and four in the right half (abusr
[0:3]) as shown in
globals and analog mux buses from being used for
interconnecting the analog blocks.
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In
multiplexers are indicated by grayed ovals and switches are
indicated by transparent ovals.
8.2 Delta-sigma ADC
The CY8C36 device contains one delta-sigma ADC. This ADC
offers differential input, high resolution and excellent linearity,
making it a good ADC choice for measurement applications. The
converter can be configured to output 12-bit resolution at data
rates of up to 192 ksps. At a fixed clock rate, resolution can be
traded for faster data rates as shown in
Table 8-1. Delta-sigma ADC Performance
Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V
8.2.1 Functional Description
The ADC connects and configures three basic components,
input buffer, delta-sigma modulator, and decimator. The basic
block diagram is shown in
muxes is delivered to the delta-sigma modulator either directly or
Document Number: 001-53413 Rev. *I
1,000,000
100,000
10,000
1,000
100
Bits
12
8
7
Continuous
M ulti-Sam ple
8
Maximum Sample Rate
Figure
8-2. Using the abus saves the analog
9
Figure
(sps)
192 k
384 k
Resolution, bits
8-4. The signal from the input
10
Table 8-1
Figure
11
PRELIMINARY
SINAD (dB)
and
8-2,
66
43
12
Figure
8-3.
13
through the input buffer. The delta-sigma modulator performs the
actual analog to digital conversion. The modulator over-samples
the input and generates a serial data stream output. This high
speed data stream is not useful for most applications without
some type of post processing, and so is passed to the decimator
through the Analog Interface block. The decimator converts the
high speed serial data stream into parallel ADC results. The
modulator/decimator frequency response is [(sin x)/x]
frequency response is shown in
Figure 8-4. Delta-sigma ADC Block Diagram
Figure 8-5. Delta-sigma ADC Frequency Response,
Normalized to Output, Sample Rate = 48 kHz
Resolution and sample rate are controlled by the Decimator.
Data is pipelined in the decimator; the output is a function of the
last four samples. When the input multiplexer is switched, the
output data is not valid until after the fourth sample after the
switch.
8.2.2 Operational Modes
The ADC can be configured by the user to operate in one of four
modes: Single Sample, Multi Sample, Continous, or Multi
Sample (Turbo). All four modes are started by either a write to
the start bit in a control register or an assertion of the Start of
Conversion (SoC) signal. When the conversion is complete, a
status bit is set and the output signal End of Conversion (EoC)
asserts high and remains high until the value is read by either the
DMA controller or the CPU.
8.2.2.1 Single Sample
In Single Sample mode, the ADC performs one sample
conversion on a trigger. In this mode, the ADC stays in standby
state waiting for the SoC signal to be asserted. When SoC is
signaled the ADC performs four successive conversions. The
(Analog Routing)
PSoC
Input Mux
Input Mux
Negative
-100
Positive
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
100
®
3: CY8C36 Family Datasheet
1,000
Buffer
Input
Input frequency, Hz
Input Frequency, Hz
Modulator
10,000
Figure
Sigma
Delta
8-5.
Decimator
100,000
SOC
Page 49 of 112
4
; a typical
12 to 20 Bit
Result
EOC
1,000,000
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