CY8C36_10 CYPRESS [Cypress Semiconductor], CY8C36_10 Datasheet - Page 99

• Manufacturer Part Number: CY8C36_10
• Manufacturer: CYPRESS [Cypress Semiconductor]

11.9.6 Phase-Locked Loop
Table 11-73. PLL DC Specifications
Table 11-74. PLL AC Specifications
Document Number: 001-53413 Rev. *I
I
Fpllin
Fpllout
Jperiod-rms Jitter (rms)
Notes
Parameter
DD
Parameter
57. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
58. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
59. Based on device characterization (Not production tested).
PLL operating current
PLL input frequency
PLL intermediate frequency
PLL output frequency
Lock time at startup
[59]
Description
Description
[57]
[57]
[58]
PRELIMINARY
In = 3 MHz, Out = 67 MHz
In = 3 MHz, Out = 24 MHz
Output of prescaler
Conditions
Conditions
PSoC
®
3: CY8C36 Family Datasheet
Min
Min
24
–
–
1
1
–
–
Typ
400
200
Typ
–
–
–
–
–
Max
Max
250
250
48
67
–
–
3
Page 99 of 112
Units
Units
MHz
MHz
MHz
µA
µA
µs
ps
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